This invention relates generally to address mode change management and, in particular, to a method, system, and computer program product for minimizing unnecessary overhead in address mode change management in a microprocessor.
In a computer architecture that supports multiple addressing modes (e.g. IBM®'s z/Architecture supports three addressing modes—24, 31 and 64-bit), these address modes affect how many effective address bits are used in instruction and operand address calculations.
Address mode (AM) updates need to be visible to instruction fetching (ifetching) and operand fetching (ofetching) for all instructions after the instruction that does the update. The easiest way to effect this is to force a “serialization exceptional condition” (serialize xcond, or xcond) after the AM-changing instruction, which causes the entire pipeline to purge and resume on the immediate-next instruction after the AM-changer. It also forces all outstanding i- and ofetches to be discarded. In addition, Xcond purges are quite costly and aren't always required.
It would be desirable to provide a way to minimize the above-stated performance impact of address mode changes.